A redundancy region having a preliminary memory cell is provided, such that if a memory cell of a semiconductor memory device or a bit line connected to the memory cell is defective, a method for redundancy remedy accesses the memory cell in the redundancy region with a memory cell address to be accessed is known to those skilled in the art.
In a non-volatile memory device, for example, a redundancy remedy function may, in addition to a column redundancy function for conducting redundancy remedy by replacing a bit line connected to a plurality of memory cells as a redundancy unit with a redundancy bit line, may have a block redundancy function, when performing batch operation such as data erase by memory block having a predetermined number of memory cells, which enables redundancy remedy by replacing the memory block as a redundancy unit with a redundant memory block. Redundancy remedy efficiency using the redundant memory block in the semiconductor memory device has a trade-off relation to increased occupied area on a chip die. Redundant memory block arrangement constitution which has been proposed will be overviewed below.
In Patent Document 1 described below, as shown in FIG. 17, a memory architecture 110 has a matrix 111 of memory cells with n×m memory sectors. The memory sectors arranged in the matrix 111 consist of vertical sector groups indicated by V1, V2, . . . , Vn and horizontal sector groups indicated by H1, H2, . . . , Hm. Row redundancy sectors R1, R2, . . . , Rn are provided to the vertical sector groups V1, V2, . . . , Vn, respectively.
Row address ADr to be accessed is supplied to a row decoder 112 and a memory matrix 114 storing a defective row address by vertical sector group. When the row address ADr is matched with the defective row address, a select signal to a redundancy cell row is outputted from the matrix 114 to the row decoder 112 and a column decoder 113. A sector including the defective row address is replaced with a redundancy sector belonging to the vertical sector group including the sector. The replacement with the redundancy sector is conducted by the vertical sector group.
In Patent Document 2 described below, as shown in FIG. 18, word line decoder WLDEC, bit line decoder ABLDEC, and source line decoder ASLDEC are provided by 16 cell arrays ACLA. The cell array ACLA has 64 sectors and two redundancy sectors along a bit line. The two redundancy sectors are arranged at both ends of the cell array ACLA.
The replacement with a redundancy sector is conducted by replacing a defective column address with a redundancy column by the cell array ACLA. A sector including the defective column address is replaced with a redundancy sector belonging to the cell array ACLA including the sector. The replacement with a redundancy sector is conducted by the cell array ACLA.
In the IEEE Document described below, as shown in FIG. 19, in a flash memory in which a memory cell array region is partitioned into four banks and peripheral circuits are arranged in the center portion interposed between the banks, four redundancy sectors are added to one corner of the center portion in which the peripheral circuits are arranged. Each of the redundancy sectors can be replaced with a memory sector belonging to any bank.
The memory cells in the redundancy sector are connected to exclusive word lines and exclusive bit lines and are controlled by exclusive row decoders and exclusive column decoders.
The above-referenced prior art documents are as follows: Patent Document 1: Japanese Unexamined Patent Publication No. 2001-229691; Patent Document 2: Japanese Unexamined Patent Publication No. 2002-269994; and Non-Patent Document: IEEE J. of Solid-State Circuits, vol. 37, pp. 1485–1492, November 2002.
In the techniques described in the above Patent Documents 1 and 2, a redundancy sector is provided by the vertical sector group (Patent Document 1) or redundancy sectors are provided by the cell array ACLA (Patent Document 2). The number of remediable access-defective portions can be increased to contribute to the enhancement of the yield of a semiconductor memory device.
Generally, access defectiveness of a memory cell in a semiconductor memory device is not constant throughout the manufacturing period and is reduced through improvement in the manufacturing process and circuit function. A number of redundancy sectors which have been necessary in the early stage of manufacturing may be unnecessary by later improvements. A number of unused redundancy sectors will be left on a chip die, resulting in increased chip size. The increased chip size means a decreased number of effective chips per semiconductor wafer. In consideration of defectiveness remedy using the redundancy sector, a decreased number of effective chips due to provision of the redundancy sector by a small unit such as the vertical sector group can increase the manufacturing cost per chip.
In the above IEEE Document, the number of redundancy sectors is limited to improve the problem of increased chip size due to unused redundancy sectors.
In the IEEE Document, the redundancy sectors are arranged in the peripheral circuit region between banks, are connected to exclusive word lines and bit lines different from those connected to the memory sectors of the banks, and have exclusive row decoders and column decoders. When the column redundancy function is provided to the redundancy sectors, the word lines and bit lines are different from those of the memory sectors of the banks. Exclusive column redundancy judge circuits must be provided.
The occupied area on a chip die on which these exclusive connections and exclusive circuits are arranged can increase the chip size. In the same manner, the manufacturing cost per chip with a decreased number of effective chips per semiconductor wafer can be increased, which is a problem.
Thus, it is desirable to provide a semiconductor memory device which can improve redundancy remedy efficiency while reducing increased chip die area and can supply a suitable voltage bias to a redundant memory block irrespective of its arrangement position and a redundancy control method for the semiconductor memory device. The present invention has been made to solve at least one of the problems of the prior art.